A. Field of the Invention
The present invention relates to a method of manufacturing a power semiconductor device such as a MOSFET, and in particular, to a method of manufacturing a super-junction semiconductor device having a super-junction structure (also called a parallel pn column structure), a drift layer which is constructed with n type columns and p type columns extending in a direction perpendicular to a principal surface of a semiconductor substrate and arranged alternately in the direction parallel to the principal surface.
B. Description of the Related Art
The following patent documents will be discussed herein:
Patent Document 1—Japanese Unexamined Patent Appn. Pub. No. 2001-119022
Patent Document 2—U.S. Pat. No. 5,216,275
Patent Document 3—International Patent Appn. Pub. WO2011/093473
Patent Document 4—Japanese Unexamined Patent Appn. Pub. No. 2012-142330
Patent Document 5—International Patent Appn. Pub. WO2010/024433
Patent Document 6—Japanese Unexamined Patent Appn. Pub. No. 2007-235080.
Semiconductor devices are generally classified into horizontal type devices having the electrodes on one side of the semiconductor substrate and vertical type devices having the electrodes on both sides of the semiconductor substrate. In a vertical semiconductor device, the direction of flow of drift current in an ON state coincides with the direction of extension of a depletion layer due to a reverse bias voltage in an OFF state. In a usual planar n channel vertical type MOSFET, a high resistaivity n− drift layer carries drift current in the vertical direction in an ON state. Consequently, a shortened current path of the n− drift layer lowers a drift resistance and thus reduces actual ON resistance of a MOSFET.
On the other hand, the high resistivity n− drift layer is depleted in the OFF state to enhance the withstand voltage. Consequently, a thin n− drift layer narrows the width of the depletion layer starting from the pn junction between a p base region and the n− drift layer and extending into the region between the drain and base, resulting in lowered withstand voltage. On the contrary, a semiconductor device exhibiting a high withstand voltage has a thick n− drift layer and a high ON resistance, resulting in large conduction loss. Thus, there is a trade-off relationship between the ON resistance and the withstand voltage. This trade-off relationship is known to be likewise held in other semiconductor devices including IGBTs, bipolar transistors, and diodes.
In order to cope with this problem of the trade-off relationship, Patent Documents 1 and 2 disclose super-junction semiconductor devices with the drift layer thereof composed of a parallel pn layer formed of repeated structure of alternately adjoined high concentration n type regions and p type regions.
FIG. 14H is a sectional view of an essential part of a conventional super-junction semiconductor device. Device surface structure 250 formed in a region of a first principal surface, which is a front surface, comprises p base region 225, p+ contact region 223, n+ source region 224, gate electrode 231, insulation film 232, and source electrode 233. In a region of a second principal surface, which is a back surface, drain electrode 211 in contact with n+ drain region 210 is provided. Parallel pn layer 150 is formed between device surface structure 250 and n+ drain region 210.
In super-junction semiconductor device 500 having the structure described above, a depletion layer expands laterally from every pn junction extending vertically in the pn layer in an OFF state. Thus, the whole drift layer is depleted even though the impurity concentration of parallel pn layer 150 is high. Consequently, parallel pn layer 150 achieves a high withstand voltage.
Two major methods are known for manufacturing super-junction semiconductor device 500. Patent Document 1 discloses a method for forming a super-junction by repeating processes of epitaxial growth and ion implantation. This method is called a multi-stage epitaxial method.
FIGS. 13A through 13F and, FIGS. 14G and 14H are sectional views illustrating a conventional method of manufacturing, in a sequence of steps, a super-junction semiconductor device according to a multi-stage epitaxial method.
(1) First, as shown in FIG. 13A, high resistivity semiconductor epitaxial layer 120 is formed on n+ silicon substrate 110.
(2) Then, as shown in FIG. 13B, phosphorus ions 121a are implanted onto a surface of the semiconductor epitaxial layer 120 to form n type implantation region 121.
(3) Then, as shown in FIG. 13C, resist 130 is applied on n type implantation region 121 on the surface of semiconductor epitaxial layer 120 and then patterned by a photolithography method.
(4) Then, as shown in FIG. 13D, boron ions 122a are implanted from the surface side of resist 130 and semiconductor epitaxial layer 120 to form p type implantation layer 122.
(5) Then, as shown in FIG. 13E, resist 130 is removed.
(6) Then, as shown in FIG. 13F, steps (1) through (5) described above are repeated six times, for example, and then semiconductor epitaxial layer 120 is formed once again.
(7) Then, as shown in FIG. 14G, a driving heat treatment process is conducted at a temperature between 1,150° C. and 1,200° C., which is higher than the temperature in the epitaxial growth process. The heat treatment process performs diffusion of phosphorus ions 121a in n type implantation regions 121 and boron ions 122a in p type implantation regions 122, and makes each of n type implantation regions 121 and p type implantation regions 122 join together in the vertical direction, thereby producing n type semiconductor layer 123, i.e., an n type column, and p type semiconductor layer 124, i.e., a p type column. The impurity concentrations in n type semiconductor layer 123 and p type semiconductor layer 124 are higher around dotted lines 140 than those in inner regions 141 between lines 140.
(8) Finally, as shown in FIG. 14H, device surface structure 250 is formed including p base region 225, p+ contact region 223, n+ source region 224, gate electrode 231, oxide film 232, and source electrode 233. Drain electrode 211 is formed on the back surface of n+ drain region 210, which is n+ silicon substrate 110. All these components are formed by processes commonly employed in manufacturing a conventional MOSFETs. Thus, a traditional super-junction semiconductor device 500 is completed.
Patent Document 2 discloses another method of manufacturing a super-junction structure in which an n type layer is epitaxially grown on an n+ substrate and a trench is dug in the n type layer. In the trench, a p type layer is epitaxially grown. This method is called a trench embedding method.
Patent Document 3 discloses a super-junction semiconductor device that improves relationship between Eoff and dV/dt. This super-junction semiconductor device comprises a high concentration layer, for example a high concentration n type semiconductor layer, in the surface region (on the first principal surface side) of the super-junction structure, that contains impurities at a concentration 1.5 to 2.0 times higher than those in the inner portion of the super-junction structure. This construction makes the extension of depletion layer in the turning OFF process difficult without changing an external gate resistance connected to the gate terminal of the super-junction semiconductor device. Thus, the trade-off relationship between the Eoff and dV/dt is improved.
Now an explanation is made on the relationship between the Eoff and the dV/dt in the turning OFF process. In order to suppress electromagnetic noise, a measure is conventionally taken in which a gate resistance, a circuit resistance, with a relatively high resistance is connected to the gate of the super-junction semiconductor device from the outside to reduce the dV/dt in a turning OFF process. An enlarged gate resistance, however, elongates the time for drawing out the charges from a gate capacitance including a mirror capacitance of the super-junction semiconductor device in a turning OFF process, resulting in increased turning OFF loss, i.e., Eoff. Therefore, the Eoff is in a trade-off relationship with the dV/dt. Patent Document 3 discloses a device structure that improves the trade-off relationship between Eoff and dV/dt by decreasing dV/dt without enlarging a gate resistance. In this device structure, a parallel pn layer of super-junction is formed by multi-stage epitaxial method and a high concentration layer is formed at the position of the top stage. Patent Document 3 also discloses another method that forms a high concentration epitaxial layer on a low concentration epitaxial layer. Then, trench embedding method is used for embedding a p type semiconductor layer in a trench to form a super-junction parallel pn layer. This forms a structure having a high concentration epitaxial layer arranged in the top portion of a parallel pn layer.
Patent Document 4 discloses a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) provided with a high concentration n type buffer layer under a parallel pn layer in order for reverse recovery current of a parasitic diode to become soft-recoverying. This buffer layer is formed by making heavy particles such as protons or helium ions become donors. These heavy particles also work as lifetime killers.
Patent Document 5 discloses lifetime control by introducing lifetime killers into a parallel pn layer of a super-junction MOSFET, which is carried out by irradiation of heavy particles such as protons or helium ions forming lattice defects. Optimization of the depth of the heavy particle irradiation allows the reverse recovery time of the parasitic diode and the leakage current to become simultaneously small.
Patent Document 6 discloses about forming a parallel pn layer long in the depth direction, which is formed by multiple times of oblique ion implantation onto a side wall of a deep trench with an aspect ratio larger than 8 and then filling the trench with a semiconductor layer of the opposite conductivity type.
However, the multi-stage epitaxial growth method as disclosed in Patent Document 3 repeats about six times, as previously described referring to FIGS. 13A through 13F, a series of four steps of: (1) epitaxial growth, (2) ion implantation, (3) patterning, and (4) ion implantation. This procedure takes a long time and raises manufacturing costs. The trench embedding method is also costly when the high concentration layer with a homogeneous impurity concentration is formed by epitaxial growth process. The epitaxial growth process is difficult to control an impurity concentration and thickness of the high concentration layer with high accuracy.
Patent Document 1 discloses a trade-off relationship between Eoff and dV/dt only about a parasitic diode and fails to mention improvement in the trade-off relationship between Eoff and dV/dt in a turning OFF process in the case of variable gate resistance of a MOSFET. Patent Documents 2, 4, and 6 fail to mention improvement in the trade-off relationship between Eoff and dV/dt in a turning OFF process in the case of variable gate resistance with a parallel pn layer having a high concentration layer disposed in an upper part of the parallel pn layer. The technique of heavy particle irradiation disclosed in Patent Document 5 is for controlling the lifetime and the document does not mention producing donors.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.